One last aspect of logic gates needs to be discussed, and that is how many inputs and outputs a gate can have, if we generalize these logic functions to more than two inputs. The number of input wires to a logic gate is called the fan-in and the number of output wires is the fan-out. There are physical and logical constraints on these.
For all gates we have discussed, there is a single logic value output, which can be channeled to several other gates as their inputs using solder points. If an output is used to drive too many inputs, the power drain will cause the signal to be attenuated. However, NIBs and NOTs, which are amplifiers, can be used to boost a signal back up to its original strength, so real circuits use NIBs and NOTs in places that might not seem logically necessary, but are required by the nature of the electronics.
The NOT and NIB gates cannot have more than one input, while the tri-state buffer must have exactly two inputs. Many of the other logic gates, have obvious generalizations to more than two inputs. Following is a three-input AND along with its truth table:
The truth table shows that the output of a 3-input AND gate is 1 only when all its inputs are 1, which is a logical generalization of the 2-input case. Similarly for OR, the output is 1 when any of its inputs is 1. Another way to find out the values of a multi-input AND or OR gate is to construct a cascaded logic circuit where all the components are 2-input gates:
Building a complete truth table would get the same answer as the above.
For XOR and XNOR, it is not as obvious what the generalization to 3 or more inputs would produce. Cascading reveals that XOR is really an odd-parity test function. Odd parity means that the total number of 1s in a sequence of bits is odd. Thus the bit string 0110100000 conforms to odd parity since there are 3 ones. The bits 0110100001 conforms to even parity, because there are 4 ones, and 4 is an even number.
The XOR gate takes in a number of bits and spits out 1 if all those bits conform to odd parity. Similarly the XNOR gate takes in a number of bits and spits out 1 if all those bits conform to even parity.
A B | A@B # of 1's Input string conforms to odd parity? --------+------------------------------------------------------- 0 0 | 0 0 (even) no, hence emit 0 0 1 | 1 1 (odd) yes, emit 1 1 0 | 1 1 (odd) yes, emit 1 1 1 | 0 2 (even) no, emit 0
(The symbol @ stands for exclusive or and means the
same as the symbol 
.)
As can be seen in the truth table for just two inputs to an XOR gate, if the bit string that is the two inputs conforms to odd parity, XOR emits 1.
An alternative way to view the multi-input XOR gate is to say that it computes the even parity bit given its inputs. That is, if there are an odd number of 1s in the input wires, XOR spits out 1 so that the three input wires and the one output wire all together have an even number of 1s. The following truth table is labeled to show this idea:
A B | A@B # of 1's To make all 3 bits conform to even parity --------+--------------------------------------------------------------- 0 0 | 0 0 (even) emit 0 0 1 | 1 1 (odd) emit 1 1 0 | 1 1 (odd) emit 1 1 1 | 0 2 (even) emit 0
Similarly XNOR tests for even parity, and it also computes the odd parity bit. However, this is only true if there is an even number of bits in the bit string! If there is an odd number, it does not compute the right values due to the fact that XNOR is really XOR followed by a NOT gate. Similarly, NAND and NOR do not cascade. If the number of bits is even, however, then negating twice gets back to the positive side, so it works out when there are an even number of bits.
Parity is different than the equivalence and not-equivalence functions that 2-input XOR and XNOR gates compute. If there are three or more bits, at least two of the bits must be equivalent to each other, so the concept of equivalence does not extend past two inputs if there are only two distinct values, as is true in Boolean land.
Fig. 1.9.3 shows a 3-input XOR, and a logic circuit that uses two cascaded XORs. The truth table for the cascaded circuit, shown below, reveals that XOR (at least for 3 inputs) either tests for odd parity, or computes the even parity bit, which are equivalent.
A B C | B@C A@(B@C) #1's in 3 inputs ---------------+------------------------------------- 0 0 0 | 0 0 0 (even) 0 0 1 | 1 1 1 (odd) 0 1 0 | 1 1 1 (odd) 0 1 1 | 0 0 2 (even) 1 0 0 | 0 1 1 (odd) 1 0 1 | 1 0 2 (even) 1 1 0 | 1 0 2 (even) 1 1 1 | 0 1 3 (odd)
Cascading does not work for NAND or NOR because the negation reverses the inputs to the next level. To cascade NAND, do not put NOT gates on any inputs except the first level. Here are the rules for multi-input NAND and NOR.
| The output of an n-input NAND is 1 unless all inputs are 1, in which case it is 0. |
| The output of an n-input NOR is 0 unless all inputs are 0, in which case it is 1. |
Here are generic truth tables to illustrate these cases:
I1 I2 I3 I4 ... In | NAND of all I's
----------------------------------------+--------------------
0 0 0 0 ... 0 | 1
0 0 0 0 ... 1 | 1
... | 1
1 1 1 1 ... 0 | 1
1 1 1 1 ... 1 | 0
I1 I2 I3 I4 ... In | NOR of all I's
----------------------------------------+--------------------
0 0 0 0 ... 0 | 1
0 0 0 0 ... 1 | 0
... | 0
1 1 1 1 ... 0 | 0
1 1 1 1 ... 1 | 0
The physics of gate construction using transistors makes it easy to construct multiple input gates unless the fan-in is too great, in which case the problems of signal attenuation set in. Today's technology permits 8-input gates without any problems. We will use them wherever convenient.