In Fig. 12.10.2, the TLB is inserted, showing how it speeds up this complex virtual memory system by bypassing the multi-step translation process if the virtual address has been translated recently.

The MMU is shown in gray. It comprises the entire virtual address translation system, except that page tables are often so large that they must be stored in RAM itself. This is why they are surrounded in yellow. However, some older systems cache the page tables in special high speed memory or registers.