To perform a read operation, the CPU takes the lead by putting an address of the desired byte on the address wires, and setting both control wires MA and RD to 1. The memory is designed to watch for MA to go high, at which point it absorbs the operation code (RD) and the address and begins to decode that address. After a delay, it puts the desired byte onto the data wires, which the CPU absorbs. In a tightly coupled system, the exact timing between the CPU and the memory is well defined and those two circuits "know" how much time they have to wait. In a more heterogeneous system, other mechanisms must be used.

During a read operation, the CPU acts as the initiator while memory always acts as the responder, even though the data is flowing from memory to the CPU during the latter part of the operation. The identification of who is the initiator and who is the responder depends upon which component starts the bus operation by putting values on the control wires. Since memory never takes the lead in this way, it is always the responder.