Practice Exercise 16 Answers
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In a certain computer, memory is byte addressable and there are
16,777,216 bytes in main memory.
a.) The CPU communicates to main memory by transferring 32 bits at a time,
one full integer or single-precision floating point number. How many wires
do there need to be in the bus? Break it down by group: data wires,
address wires, control wires.
16 Megabytes requires 24 address wires since 224 = 16 meg.
32 bits of data require 32 data wires, and there must be at least 2
control wires for memory (MA and RD). Thus there needs to be
24 + 32 + 2 = 58 wires in the bus.
b.) Suppose there can only be 8 data wires. How much slower will the system
be, at least in terms of transferring data between memory and the CPU?
8 data wires means that the 32 data bits will have to travel over the bus
8 bits at a time, so it will be 4 times slower.
c.) What do we call this wire-sharing technique?
This is called multiplexing.
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An alternative to dynamic bus arbitration, as implemented by a bus
control arbiter, is static bus arbitration, where there is a fixed
"pecking order" among the devices which act as bus initiator.
That is, if device A and
device B both contend to be bus initiator, one of them will win simply because
there is predetermined priority to it. What kind of circuit could be used
for this type of arbitration? (Hint: Exercise 4)
We would need a priority encoder.
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A clock generates pulses at the frequency of 100 MHz (megahertz). What
is the period of this timing signal? (This is the length of time between
the rising edge of the clock signal to the next rising edge.)
frequency = 100 MHz, period = 1/100,000,000 = .00000001 sec (10 nsec)
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What would be the frequency of a clock whose period is 70 nsec? Express
in both Hz and MHz.
70 nsec = 70 billionths of a second or
70 x 1 / 1,000,000,000 = .00000007 sec.
1 / .00000007 sec = 14,285,714 Hz (cycles per second).
This is about 14.3 MHz.
(In the world of frequencies, a megahertz is 1,000,000 Hz,
not 1,048,576 Hz, like a megabyte is.)
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Refer to the diagram of a synchronous read transaction in the text.
Suppose that the bus clock is running at 1 MHz. How long would one memory
read require in
a.) seconds
1 MHz means 1,000,000 cycles per second, so each T cycle is 1
millionth of a second, and two of them would be .000002 sec.
b.) p where p is the period of the clock signal
This is easy, since it is obviously 2p.
c.) Judging from the spacing in the figure, approximately how long (in both
p and seconds) does memory require to actually fetch the desired value from
its memory and put it on the outgoing data wires?
It looks like the memory gets all its inputs about 25% of the way
through cycle T1, and that the answer is available about 25%
of the way through cycle T2. This means that it takes one time
period (1p) or .000001 sec (one millionth of a second).
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Below are timing constraints for an asynchronous bus.
These constraints define the order and spacing of the various
events in a single transaction.
The minimum time between events must be nsec
e1 and e2 40
e2 and e3 10
e3 and e4 15
e4 and e5 10
e5 and e1 (the next cycle) 7
a.) How long does one full read take? This is the time it takes from the
start of one read transaction to the start of the next.
40+10+15+10+7 nsec = 82 nsec = .000000082 sec
b.) How many read transactions per second can this system sustain?
1 / .000000082 = 12,195,122 reads per second.
Suppose there was a synchronous bus running at 20 MHz that designers
were considering as an alternative. How many read transactions per second
could it sustain?
Since our bus structure requires 2 cycles for one read, the
synchronous bus running at 20 MHz would be able to sustain
10 million reads per second.