Practice Exercise 16
  1. In a certain computer, memory is byte addressable and there are 16,777,216 bytes in main memory.
  1. The CPU communicates to main memory by transferring 32 bits at a time, one full integer or single-precision floating point number. How many wires do there need to be in the bus? Break it down by group: data wires, address wires, control wires.

     

  2. Suppose there can only be 8 data wires. How much slower will the system be, at least in terms of transferring data between memory and the CPU?

     

  3. What do we call this wire-sharing technique?
  1. An alternative to dynamic bus arbitration, as implemented by a bus control arbiter, is static bus arbitration, where there is a fixed "pecking order" among the devices which act as bus initiators. That is, if device A and device B both contend to be bus initiator, one of them will win simply because there is predetermined priority to it. What kind of circuit could be used for this type of arbitration? (Hint: Exercise 4)
  1. A clock generates pulses at the frequency of 100 MHz (megahertz). What is the period of this timing signal? (This is the length of time between the rising edge of the clock signal to the next rising edge.)
  1. What would be the frequency of a clock whose period is 70 nsec? Express in both Hz and MHz.
  1. Refer to the diagram of a synchronous read transaction. Suppose that the bus clock is running at 1 MHz. How long would one memory read require in
  1. seconds

     

  2. p where p is the period of the clock signal

     

  3. Judging from the spacing in the figure, approximately how long (in both p and seconds) does memory require to actually fetch the desired value from its memory and put it on the outgoing data wires?
  1. Below are timing constraints for an asynchronous bus. These constraints define the order and spacing of the various events in a single transaction. 
          The minimum time between events           must be     nsec
                             e1 and e2                       40
                             e2 and e3                       10
                             e3 and e4                       15
                             e4 and e5                       10
                             e5 and e1 (the next cycle)       7
  1. How long does one full read take? This is the time it takes from the start of one read transaction to the start of the next.

     

  2. How many read transactions per second can this system sustain?

     

  3. Suppose there was a synchronous bus running at 20 MHz that designers were considering as an alternative. How many read transactions per second could it sustain?