Section 18.7
Review Questions
Memory-mapped I/O
  1. What are some benefits to memory mapped I/O?
answer...
1. it creates an unlimited supply of ports
2. it does not require explicit I/O instructions such as IN and OUT
3. it treats I/O like memory or regular variables, easier to use
  1. Name a chip that has no explicit I/O instructions.
answer...
Motorola 68000 and its descendants
  1. What term do we use for explicit I/O using IN and OUT instructions?
answer...
isolated I/O
  1. Are the memory words assigned to a particular I/O device contiguous?
answer...
Yes, they are all grouped together in a small region of RAM
  1. How is the actual physical memory involved when the CPU issues an I/O instruction to a peripheral via memory-mapped I/O?
answer...
The main memory is never actually involved at all! The device intercepts the signals from the system bus and the main memory ignores them.
  1. What kind of circuit is needed to decide who should pay attention to which signals or commands on the system bus?
answer...
decoders
  1. In addition to the above circuit, what wire must exist to alert the device that it should pay attention to the commands on the system bus?
answer...
device active, similar to MA (memory active)
  1. If 8 words of memory are allocated to a device, what size of decoder is needed in the device?
answer...
3×8
  1. Draw a logic diagram showing the gates needed to set the device active wire high for a device whose 8 memory words go from address 00001000 to 00001111.
answer...
  1. What differences are there in the assembler program that communicates with peripherals? We are comparing memory-mapped I/O to isolated I/O.
answer...
There is no real difference in the algorithm, but instead of using explicit IN and OUT instructions, memory LOAD and STORE instructions are used.
  1. In the following program, which instructions check to see if the data ready bit is turned on? 
     CHECKCTL: LOD  1000
               SUB  "01"b
               JNZ  CHECKCTL
               LOD  1001
               STD  X
               LDI  "11"b
               STD  1000
               JMP  CHECKCTL
answer...
CHECKCTL: LOD  1000      ;read data ready bit from control reg.
          SUB  "01"b     ;compare to 01b
          JNZ  CHECKCTL  ;if not equal jump up to top of loop
  1. In the above program, how does the CPU tell the peripheral that it received the data byte and the peripheral should continue on to the next byte?
answer...
          LDI  "11"b     ; get ready to write 1 into data accepted bit
          STD  1000      ; write to control register