Multiple Bank Memory Organization

Memories in a real computer use a variety of tricks to reduce the explosion of wires. Another common method is to break up memory into separate banks and then select from the appropriate bank. The number of banks is usually power of 2 so that 1 or more of the address bits can be used to select which memory bank is turned.

Fig. 1 shows a 32-word memory of 5-bit words broken into 2 banks:

The lower four bits of the MAR are decoded and sent to both banks simultaneously. But the uppermost bit of the MAR decides which bank is "turned on" and which is ignored. If the operation is a read, only the selected bank puts its value onto the MBR bus. If the operation is a write, only the selected bank changes its flip-flops. The actual connection between the bank selection wire and the flip-flops is not shown in this diagram.

If there are 4 or more banks, the uppermost bits must be sent into a decoder. The following picture shows 4 banks of 16 words each. Many details are omitted: