The memory organization shown for RAMs and ROMs above suffers from a problem of scale: it works fine when the number of words in the memory is relatively small but quickly mushrooms as the memory is scaled up or increased in size. This happens because the number of word select wires is an exponential function of the size of the address. Suppose that the MAR is 10 bits wide, which means there are 1024 words in the memory. The decoder will need to output 1024 separate lines. While this is not necessarily terrible, increasing the MAR to 15 bits means there will be 32,768 wires, and 20 bits would be over a million.

Fig. 1 shows a 16-word memory of 5-bit words using the conventional organization:

One way to tackle the exponential explosion of growth in the decoder and word select wires is to organize memory cells into a two-dimension grid of words instead of a one-dimensional arrangement. Then the MAR is broken into two halves, which are fed separately into smaller decoders. One decoder addresses the rows of the grid while the other decoder addresses the columns. Fig. 2 shows a 2.5D memory of 16 words, each word having 5 bits:

Each memory cell has an AND gate that represents the intersection of a vertical wire from one decoder and a horizontal wire from the other. The output of this AND gate is the line select wire.

In the above example, the total number of word select lines goes down from 16 to 8. (There are four wires coming from each of two decoders.) If the MAR had 10 bits, there would be 1024 word select wires in the traditional organization, but only 64 in the 2.5D organization because each half the MAR contributes 5 address bits, and 2⁵ = 32.

Just to continue the illustration, if the MAR had 32 bits, the traditional organization would require about 4 billion word select wires. If 2.5D organization were used, the MAR would split into two 16-bit sections, each creating 2¹⁶, or 65536, wires. Since there are two of them, this creates 131,072 wires. The ratio of these two sizes is 0.000030518 or about 0.003%. Three thousandths of one percent! What a savings!

The usual terminology for a 2.5D memory is 2¹/² memory, but this is hard to write. Nobody is sure why it is called a two and a half dimensional thing, unless it is perhaps because an ordinary memory is obviously two dimensional and this one is not quite three dimensional.

In a real circuit, the wires are cleverly laid out so that they go around, not through, flip-flops, unlike our schematic diagram.

2.5D memory organization is almost always used on real memory chips today because the savings in wiring and gates is so dramatic. Real computers use a combination of banks of memory units, and each memory unit uses 2.5D organization.