When a program does arithmetic, it often has to make decisions based on the results: whether overflow occurred, if the result is 0 or negative, if the result is positive, and so forth. Thus, most computers have four bits coming out of the adder which give this kind of information. These are:
| Carry bit | C | if there was a final carry out, this bit is 1. This signals overflow if the two operands are unsigned. |
| Negative bit | N | if the result of the addition is negative assuming 2's complement, this bit is 1. |
| Overflow bit | V | if there was an overflow after adding two 2's complement numbers, this bit is 1. |
| Zero bit | Z | if the result of the addition is 0 (all 0s), this bit is 1. |
These bits are computed in the following ways. First, the carry bit is the final carry out of the adder circuit. It also stands for overflow when the two values that were added are considered to be unsigned binary numbers, not 2's complement signed binary numbers. Thus, the C bit is sometimes called unsigned overflow.
Next, the negative bit is nothing more than the output of the MSB (most significant bit) of the adder.
The zero bit indicates whether the result of addition is 0 or not. The computer feeds all the outputs of the adder into a big NOR gate (or a cascaded series of ORs followed by a NOT). If any wire has a 1, the output is 0. But if all the wires have 0s, the output of the NOR is 1. The use of 1 to indicate "zero" is a bit confusing since we might expect 0 to be on the 0 wire. However, think of 1 as true and 0 as false. So if Z is 1, then the Z condition is true, namely that the output of the adder is 000...0.
The overflow bit is the hardest to understand, since it is the exclusive or of the final carry out (the C bit) and the carry out of the second to last bit. Another way to compute this is to note that overflow could only occur if both addends had the same sign. If the N bit of the result is different from the sign of the addends, then overflow has resulted. It is possible to show that these two conditions are equivalent.
Fig. 6.6.1 shows the adder using the box diagrams of Chapter 4 and how the four condition bits CNVZ are created by running the outputs of the adder through various gates, as described above.
