In the CSC-1, a hardware DFA manages the control points. The DFA encodes all the instructions in the machine language given in section 3 above, as well as every aspect of the fetch/decode/execute cycle. State 0 is the initial state that the computer is in just as it is starting the next instruction. In that state it would allow the PC's value to be copied into the MAR. Then it goes to state 1, where it turns on MA, turn off WR, allowing the memory to fetch the next instruction. In state 2, the new value in the MBR, the next instruction, is copied into the IR register. Some nodes have unlabeled arcs between them, and there is such an arc between state 0 and state 1, and again between state 1 and state 2. If an arc is unlabeled, it means that the device can go from the initial state to the next state without sensing any conditions or getting "permission" from any other circuit. State 1 follows state 0, no matter what. In a hardware DFA used in a computer's control unit, there needs to be a pause of time between states to allow these circuits to function properly.

When CSC-1 leaves state 2, it could go to one of several states, depending upon which type of instruction. If the instruction has an operand, such as ADD or LOD, then the operand fetch stage has to be entered, so the IR has to be copied into the MAR. But if the instruction has no operand, a different state will be entered. Ultimately, the movement from these states to the next states depends on which instruction is being executed.