By now we are wondering how any circuitry could possibly manage all these control points for such a complex instruction set. It is not merely a question of which wires to turn on, given, say the ADD instruction, but they must be turned on and off in a certain sequence and at certain times. Computer designers have to worry about waiting the proper amount of time for the memory to do its operation, for values to emerge from decoders, for bits to latch into flip-flops, and for many other things.
One way to manage this intellectual challenge is to resort to a mathematical construct called a DFA, or deterministic finite automaton. A DFA is a graph, which is a set of nodes and arcs that have labels. A node is a circle and represents a state, while an arc is an arrow, or directed line, between nodes, which represents an input or a condition. Fig. 7.7.1 is a typical DFA.
Each state has a number: 0, 1, 2 and 3. Between two states there may be 0 or more arrows, each having a label.
There are several ways of interpreting DFAs. One of these is helping programs to recognize correctly formed expressions or linguistic utterances. In this course, we will use them to describe states of a system. For example, suppose that this DFA controls a house's furnace. State 0 might be the state the furnace is off. Input a represents a reading from the thermostat, saying that it is too cold in the house. State 1 says the furnace is firing up. When another sensor inside the burner section says that it is hot enough, it sends the signal "b" which causes the furnace to go into state 2: the blower is turned on. Input d might be another reading from the thermostat, saying the house's air is still below the desired temperature, which causes the furnace to keep running. Finally, input c might be a reading from the thermostat saying it is finally toasty in here, upon which cue the furnace goes into state 3. State 3 might represent a cooling down period -- the furnace cannot start burning again right away for safety reasons. If the sensors determine that it is still too cold, input c, the furnace goes back to state 1 and turns the burners back on, while if it is warm enough, the furnace goes back to sleep, state 0.
In the CSC-1, a hardware DFA manages the control points. The DFA encodes all the instructions in the machine language given in section 3 above, as well as every aspect of the fetch/decode/execute cycle. State 0 is the initial state that the computer is in just as it is starting the next instruction. In that state it would allow the PC's value to be copied into the MAR. Then it goes to state 1, where it turns on MA, turn off WR, allowing the memory to fetch the next instruction. In state 2, the new value in the MBR, the next instruction, is copied into the IR register. Some nodes have unlabeled arcs between them, and there is such an arc between state 0 and state 1, and again between state 1 and state 2. If an arc is unlabeled, it means that the device can go from the initial state to the next state without sensing any conditions or getting "permission" from any other circuit. State 1 follows state 0, no matter what. In a hardware DFA used in a computer's control unit, there needs to be a pause of time between states to allow these circuits to function properly.
When CSC-1 leaves state 2, it could go to one of several states, depending upon which type of instruction. If the instruction has an operand, such as ADD or LOD, then the operand fetch stage has to be entered, so the IR has to be copied into the MAR. But if the instruction has no operand, a different state will be entered. Ultimately, the movement from these states to the next states depends on which instruction is being executed.
Fig. 7.7.2 below shows a rough outline of the CSC-1's DFA. It is not complete.
Coming out of the IR are wires that have a binary number on them, the opcode. These wires go into a decoder that sets 1 and only 1 of its outputs to 1. This output wire corresponds exactly to the one of the CSC-1's instructions, so these wires can be labeled with their machine instructions. Fig. 7.7.3 shows this decoding. Remember that the first 8 bits of the IR, not merely the first 4, determine which operation is being done.
These wires are used in combination with other wires by ANDing them together to set the appropriate control points at the appropriate times. The sequencing of the DFA (this step comes after this one...) is what imparts the timing to the instruction, while the output of the operation decoder is what causes the right action to be performed.
In order to keep the computer moving from one state to another in a timely fashion, the control unit has a clock which emits a regular series of pulses. These pulses are sent through various delay gates and used by the hardware DFA to make transitions to the next state after a measured amount of time. The bus and other devices, like I/O controllers, have their own clocks that are not linked into the main computer's clock.
When a computer's clock speed is advertised, such as a 120 MHz Pentium, it is the speed of the controlling DFA clock which is being touted. Another name for cycle is Hertz, in honor of a German physicist, Heinrich Rudolf Hertz (1857-1894) who worked on electromagnetic phenomena. One Hertz, abbreviated as Hz, is one cycle per second, so 120 MHz (pronounce "megahertz") is 120,000,000 cycles every second. Of course, one complete machine instruction may require 100 cycles, so the computer is really doing 1,200,000 instructions per second. To speed up the computer, either increase the clock speed or shorten the instruction so that fewer cycles are needed to perform each machine instruction.
Clocks in computers are created by applying electric current to tiny quartz crystals which vibrate with a regular frequency when current is applied to them. This vibration can be used to raise and lower voltages in wires.
