Section 7.6
Review Questions
Example of control points and the fetch/decode/execute cycle
-
In the following picture of the CSC-1, what number will get added to
the value in A?
answer...
46
-
In the following picture, what instruction will get executed next?
answer...
SUB
-
Given the following picture, what stage has just finished?
A's initial value was 23.
instruction fetch
operation decode
operand fetch
execute
answer...
operand fetch
-
Given the following picture, what stage has just finished?
A's initial value was 23.
instruction fetch
operation decode
operand fetch
execute
answer...
instruction fetch
-
Given the following picture, what stage has just finished?
A's initial value was 23.
instruction fetch
operation decode
operand fetch
execute
answer...
execute
-
Given the following picture, what stage has just finished?
A's initial value was 23.
instruction fetch
operation decode
operand fetch
execute
answer...
operation decode
-
Which registers does the MBR's output go to? Circle all that apply.
A TMP IR PC S MAR
answer...
A, TMP, IR
-
Why do the IR and TMP registers have no muxes controlling their inputs?
answer...
because they only have 1 input path
-
Which register(s) would the following instructions change?
Circle the correct one(s).
ADD: A TMP PC IR S
SUB: A TMP PC IR S
LOD: A TMP PC IR S
STD: A TMP PC IR S
JMP: A TMP PC IR S
CAL: A TMP PC IR S
A2S: A TMP PC IR S
S2A: A TMP PC IR S
LDS: A TMP PC IR S
STS: A TMP PC IR S
answer...
ADD: A TMP PC IR
SUB: A TMP PC IR
LOD: A PC IR
STD: PC IR
JMP: PC IR
CAL: PC IR
A2S: PC IR S
S2A: A PC IR
LDS: A PC IR
STS: PC IR