This file shows how to define the various control wires in terms of other wires (mostly state wires, but also output of the ALU.) This is the same information conveyed in dfa.html, but inverted so that it can be implemented using Boolean logic gates.

To get the following, take dfa.html and invert it so as to show when the various control wires are set to 1. For example, MARLD is set to 1 only when S2=1 or S9=1 or S28=1 or S35=1. This can be obtained from the dfa by looking for all states that have MARLD=1 in them, and then pasting them together using ORs.

The inverted DFA is ultimately the way that the actual printed circuits or chip would be manufactured. In other words, the dfa is just a "worksheet" that allows us to construct this set of logic expressions. Then these logic expressions are turned into actual logic circuits for use in the machine.

The state transitions in the DFA are also encoded directly into logic circuits, too. Thus, in state S8, "1->S9" is turned into an delay gate that set S9=1, after a suitable delay.

Not shown is the instruction decoder which sets the wires NOP, AND, ADD, HLT, etc. given the contents of the IR.

MARLD = S2 | S9 | S28 | S34 | S40
MBRLD = S4 | S11 | S30 | S36 | S42
MA = S3 | S10 | S31 | S37 | S41
WR = S31 | S37
ALD = S16 | S25 | S44 | S50
SLD = S47 | S53
TMPLD = S13
IRLD = S5

F2= S18 | S19 | S22
F1= S19 | S20 | S21
F0= S18 | S21

SH1= S52
SH0= S53

MARMUX1= S33 | S39
MARMUX0= S1

MBRMUX1= S3 | S10 | S41
MBRMUX0= S29 | S35

AMUX1= S24 | S49
AMUX0= S24 | S43

PCMUX = S54 | S57 | S59 | S61 | S63 | S65 | S67
PCLD = S6 | S55 | (S58 & C) | (S60 & N) | (S62 & ~N & ~Z) | (S64 & V) | 
       (S66 & Z) | S68
PCINCR = S7

SMUX= S46


Fixed Oct. 7, 2002