Here is how the four stages of the instruction cycle line up against the above sequence:

• Lines 1 through 7 implement the instruction fetch stage.
• The instruction decode stage is implicitly done after line 6.
• Lines 8 through 13 implement the operand fetch stage.
• Line 14 implements the execute stage, telling the adder which of its several functions to perform.
• Some architectures make explicit a storeback stage where the result of the computation is put into its destination. In the CSC-1, the values often go back into the A register, so lines 15 through 17 could be thought of as the storeback stage.