Step 8 begins the operand fetch stage. First MAR-MUX is set to 0 so that the output of the IR register is copied into the MAR. Remember that the low 12 bits of the IR register is the operand address. Next MAR-LD is strobed to latch this new value in steps 9 and 10. Memory is turned back on in Step 10 and the MBR is set to accept the memory's output, which is latched into the MBR's flip-flops by Steps 11 and 12.

Once the operand is in the MBR, it must be copied into the TMP register, which is done by strobing TMP-LD in steps 13 and 14. TMP's input comes only from the MBR, reinforcing the notion that TMP might be omitted entirely and the MBR could be used as the second operand. If this were so, Step 13 could be omitted entirely and F=101 and SH=00 could be added to Step 12 thereby saving some time. Nevertheless, we will stay with the diagram as we have it.