Let's go through ADD and STS using the CSC-2 configuration.

First, the instruction fetch stage will be similar for all CSC-2 instructions. We need to move the PC into the MAR and then request a memory read. This is done by setting the A decoder to 2, since PC is register number 2. The B decoder can be set to anything since the ALU function we will select is identity A, which copies only the A output to the shifter. The shifter is told to do nothing and the register is loaded. The C decoder is set to 6, which is the number of the MAR. Then MA is set to 1 and WR to 0 and the hardware waits for memory to fetch the value and copy it into the MBR. The MBR's mux is set to 1 in order to select the value coming from memory instead of the C bus.