We call one complete movement of data from the registers, through the ALU and shifter, and back into one of the registers, one cycle of the main data path. The "machine instructions" of the CSC-1 would typically require several main data path cycles if the CSC-2 setup is used. Here is what would be needed for the ADD instruction:

MAR <- PC        instruction fetch
PC <- PC + 1     advancing program counter
IR <- MBR        saving the opcode
MAR <- IR        operand fetch
A <- A + MBR     main addition step, storeback

No fewer than 5 cycles are needed, which argues that the main data path be as short as possible and the adder as fast as possible. If the PC gets back its dedicated INCR wire, one complete cycle could be saved, making ADD faster.