There is yet another level at which all machine instructions of the CSC-1 need to be described, which is down to the actual wires: what gets turned on and off, and when. These wires, such as the LD and MUX wires and the ALU and shifter control inputs, are often called control points because they are the places where the operation of the CPU is controlled.
Let us go through some of the mechanisms by which elements of RTL are implemented using the CSC-1 control points. First, whenever a register appears on the left side of the copies operator (<-) its LD wire is set high. Thus, A <- S implies that A-LD is 1.
Next, whenever a register's value or memory's data output appears on the right side of the copies operator, the appropriate mux value appears on the mux control wires for the register on the left hand side that select that register's value. Again, A <- S implies that A-MUX1 and A-MUX0 are set appropriately, since the S input to A-MUX is labeled 2 (10 in binary), requiring A-MUX1=1 and A-MUX0=0
Also, the ALU and shifter control inputs are set appropriately whenever operators appear in RTL statements. Thus, A <- A + m[x] implies that 101 appears on the F2F1F0 control wires because 101 is the code for binary addition.
Next let's look at the conditional jumps, those whose RTL use if statements such as JZ:
if Z=1 then PC <- x
The Z wire is ANDed with the instruction wire for JZ coming from the operation decoder. Only if both the JZ wire and Z are high will PC-LD and PC-MUX be set to 1, thereby allowing IR's 12 bits to be copied into PC. Since PC is 16 bits long, the upper 4 flip-flops are always loaded from a wire that always has logic 0. PC could have been made to be only 12 bits wide, but sometimes it is simpler to reuse basic components and just rig them up to act special in special cases, such as the PC.
Finally, the notations ... <- m[x] and m[x] <- ... require more explanation. The output of memory is never copied directly into any register except MBR, so the load instructions that copy m[x] into A are really more complex in that they first cause the value to go from memory to the MBR, and then from the MBR to A. The reverse happens when A's value is stored into memory.
In all of these cases dealing with memory, the first step is to load the MAR with x or S and set the two memory control wires MA and WR. If the operation is write, MBR is also loaded at the outset for either A or IR. After a delay, the output of memory is copied into the MBR, which is then copied into its final destination. These operations have to be carefully timed because the memory must be given enough time to retrieve or store values. Also, when m[x] is used as an operand in an arithmetic or logical operation, the value is really coming from the TMP register, which received a copy of the MBR after the memory read. Another possibility for the circuit designers would have been to let MBR act as the other input to the ALU, thereby avoiding a TMP register altogether.