Quiz 8.4

DIRECTIONS: Read each question carefully. Then click on the dot next to the answer that most closely fits the question. Try to answer all questions on this quiz and when you are done, click on the grade me button at the bottom.

Coverage: Section 8.4

  1. Which CSC-1 below instruction is encoded into binary as 
              0011 0000 0000 1100
    The 16 bits of the instruction have been broken into 4-bit chunks for easier reading.
LDI 12
NOP
ADD 12
RET

  1. If 0100 is the opcode for SUB, what is the value of x in the following CSC-1 instruction? 
              0100 0000 0000 0100
    4
    1024
    2048
    0

  1. If a CSC-1 instruction has an operand, how many bits long is it?
14
4
11
12

  1. Which is the final stage in the fetch/decode/execute cycle?
storeback
operand fetch
execute
instruction decode

  1. For many CSC-1 instructions, where is the result placed?
memory
A
S
PC

  1. To shorten some instructions' control point sequences, we could do away with which register and use the MBR directly in its place?
MAR
A
TMP
IR The following questions use the control point sequence for the ADD instruction, copied here for your convenience: 
                1.     MAR-MUX=01
                2.     MAR-LD=1
                3.     MAR-LD=0;  MA=1;  WR=0;  MBR-MUX=10
                4.     MBR-LD=1
                5.     MBR-LD=0;  MA=0;  PC-INCR=1;  IR-LD=1
                6.     IR-LD=0;  PC-LD=1
                7.     PC-INCR=0;  PC-LD=0
                8.     MAR-MUX=00
                9.     MAR-LD=1
               10.     MAR-LD=0;  MA=1;  WR=0;  MBR-MUX=10
               11.     MBR-LD=1
               12.     MBR-LD=0;  MA=0
               13.     TMP-LD=1
               14.     TMP-LD=0;  F=101;  SH=00
               15.     A-MUX=00
               16.     A-LD=1
               17.     A-LD=0

  1. At what step does the actual addition start?
5
14
15
16

  1. Where is the operand fetch stage, where the operand is actually copied out of memory?
Steps 10-11
Steps 3-4
Steps 1-3
Steps 12-13

  1. What could be considered the storeback stage?
Steps 10-11
Steps 12-13
Steps 14-15
Steps 15-17

  1. Which lines cause the computer to set itself up for the next instruction in sequence?
PC-INCR and PC-LD
MAR-LD and MBR-LD
S-LD and SMUX
A-LD and TMP-LD