Quiz 8.8

DIRECTIONS: Read each question carefully. Then click on the dot next to the answer that most closely fits the question. Try to answer all questions on this quiz and when you are done, click on the grade me button at the bottom.

Coverage: Section 8.8

  1. The number of registers in a computer like the CSC-2 determines how many register address wires are needed. If there are n registers, how many wires must there be?
log2n
2n
2n
n÷2

  1. Which of the following sequences of RTL statements is the correct one that implements the ADD instruction in the CSC-2? 
     MAR <- PC
     PC <- PC + 1
     MAR <- IR
     IR <- MBR
     A <- A + MBR


     PC <- PC + 1
     MAR <- PC
     MAR <- IR
     IR <- MBR
     A <- A + MBR


     MAR <- PC
     PC <- PC + 1
     IR <- MBR
     MAR <- IR
     A <- A + MBR

  1. The control points that implement these RTL instructions usually include the same set of wires since the nature of the main data path of the CSC-2 dictates that all instructions cause data to flow through the machine in about the same way: out the registers, onto the operand buses, through the ALU, shift and into the result register, and then onto the destination bus and back into a register (or memory). Which of the these RTL statements for ADD would not have to include a valid specification for the B bus? (Not all the RTL statements of ADD are given.)
MAR <- PC
PC <- PC + 1
A <- A + MBR
all of the above

  1. Which of the following RTL statements uses a hard-wired register?
MAR <- PC
PC <- PC + 1
A <- A + MBR
all of the above

  1. Which of the following RTL statements cause RESULT-LD to be set to 1?
MAR <- PC
PC <- PC + 1
A <- A + MBR
all of the above

  1. The LDI instruction (load immediate) just copies the lower 12 bits of the instruction into the A register. Which setting of F would be needed for this?
F=0 (identity A)
F=1 (unused)
F=5 (A + B)
F=3 (A or B)

  1. The PC register in the CSC-2 is no longer a super-register, meaning it does not have the PC-INCR wire or the PC-CLR wire anymore? Why not? Is it still necessary to bump up PC's value by 1 for a sequential program?
no, the CSC-2 does not go through the program in sequential fashion like the old CSC-1
yes, this is a flaw in the CSC-2's design
the controller takes over this function and adds 1 to the PC in a way not shown on the diagrams
incrementing PC can be accomplished by adding PC to the constant register 1

  1. Which RTL sequence would implement STS? (Notice that we have to resort to actually showing two control point assignments, namely MA= and WR=, because there is no convenient way to write this in RTL.) 
     MAR <- PC
     PC <- PC + 1
     IR <- MBR
     MAR <- MAR
     MBR <- A
     MA=1 WR=0


     MAR <- PC
     PC <- PC + 1
     IR <- MBR
     MAR <- A
     MBR <- S
     MA=1 WR=1


     MAR <- PC
     PC <- PC + 1
     IR <- MBR
     MAR <- S
     MBR <- A
     MA=1 WR=1
Questions 9 and 10 use the following RTL sequence for the LOD instruction: 
          1.  MAR <- PC
          2.  PC <- PC + 1
          3.  IR <- MBR
          4.  MAR <- IR
          5.  MA=1 WR=0
          6.  A <- MBR

  1. Which statements comprise the instruction fetch stage that is common to all instructions?
Steps 1-2
Steps 1-3
Steps 1-4
Steps 2-3

  1. Which statements comprise the operand fetch stage?
Steps 2-4
Steps 4-5
Steps 4-6
Steps 5-6