Section 8.8
Review Questions
Control Points for the CSC-2
-
In the CSC-2, if we wish to run some values through the ALU just to set the
condition codes but we do not want to actually change the value in any
register, what register should we specify as the destination?
answer...
+1, because it can't be changed, so any input to it is ignored
-
Why is it possible in the CSC-2 to let the PC be a regular register, not
a "super register"?
answer...
because we can use the +1 register and the ADDER to achieve the same effect
of adding 1 to the PC's contents
-
What is involved with one cycle of the main data path? Where does
the data come from, through which components does it flow, and where does it
end up?
answer...
data comes from 1 or 2 registers whose contents are placed onto the A and
B buses, then it runs through the ALU/shifter, and then waits in the result
register. Finally it is gated on the C bus and then stored into the
destination register.
-
How many cycles of the main data path are needed for machine instructions?
Just 1, 2, several?
answer...
at least 4, probably more
-
Which computer do you suppose would be faster?
CSC-1 CSC-2
answer...
CSC-1 because there are fewer movements of data
-
Below is the RTL for the five main data path cycles for the ADD instruction
in the CSC-2. Put them in the right order by writing 1 next to the first,
2 next to the second, and so on.
________ IR <- MBR
________ MAR <- PC
________ A <- A + MBR
________ PC <- PC + 1
________ MAR <- IR
answer...
___3____ IR <- MBR complete instruction fetch
___1____ MAR <- PC instruction fetch
___5____ A <- A + MBR execute
___2____ PC <- PC + 1 PC increment
___4____ MAR <- IR operand fetch (follow with Mem read)
-
Which of the five steps in the above could be moved to a different place in
the ordering without affecting the result?
answer...
step 2, PC increment