Section 16.5: Multiple bus initiators and Arbitration (Frame 8)                     [prev][home][next]

When a would-be bus initiator is denied use of the bus, it must wait until the current bus initiator is finished with its bus transaction, which might consist of several steps, as we saw above in the memory read scenario. The slighted initiator is usually in an electronic state where nothing can happen until the bus grant wire goes high, so it automatically waits (and waits "patiently", if anthropomorphic emotions can be attributed to wires and gates!) until the arbiter gives it control.