The way this asynchronous read operation works is that the CPU becomes the bus initiator after the arbiter has granted permission to do so. It puts the address on the address wires and sets RD to 1 to request a read. Then it asserts MSYN, which stands for "Master Synchronization," at time t₁. This is the electronic form of a phone ringing, waking all the responders up and telling them that there's work to be done. (Note the lamentable use of old terminology, but the acronym is explained to demystify it.)

Exactly which responder does the work is indicated by the address wires. When the right responder (in this case main memory) figures out what to do, it starts to do it, and to finish the job as soon as possible.

When it is done, at the earliest possible moment, t₂ in the above diagram, it signals the initiator by setting SSYN (slave synchronization) high. The initiator sees this is high and then latches the data wires into its registers. At t₃, the initiator turns off MSYN which is a signal to the responder that the initiator received the value and the responder can (temporarily) go back to an idle state. At t₄ all other lines of the bus are cleared in preparation for the next bus transaction, which cannot start until both MSYN and SSYN are both 0 again. This is the signal to the next bus initiator that the bus is now free and ready to use.