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In Fig. 16.7.2 we see the same timing diagram for an asynchronous read, except that the causal relationships between the turning off and on of the signals are shown.
Each of these events is numbered. e1 is when the initiator turns on MSYN, declaring that all the data and address wires are ready to go and that the main memory should begin its work immediately. e2 is when the memory puts a valid data item on the bus, which is of course caused by the initiator's request. This event, e2, in turn causes SSYN to go to 1, which is used as a signal to say that the data is ready to be read off the data wires. Eventually, the initiator latches the data value and drops MSYN as a signal that it has got it. This is event e4, which causes the responder to know that its work is done, so it drops SSYN, event e5. As long as all the causal relationships are preserved, it doesn't matter how short or how long the stretch of time is between events in an asynchronous bus. |
