Let's analyze the two memory cycles shown in Fig. 5.12.1. The first is a write operation and the second is a read operation, although it would be possible to have two or more writes in a row, or two or more reads in a row.

For a write, the computer must first store some new value into the MBR. This is shown by strobing MBRLD, after which time MBR's output lines have valid data on them. WR must be 1 before the strobe, as can be seen from Fig. 21, where WR is ANDed with the wire from the system registers before being input to the MBR's flip-flops. A short while after the MBR gets a new input value, its output wires, the RI (RAM Input) wires, will have the right values.

At the same time that the MBR is being loaded with the value to be written to memory, the address can be stored into the MAR telling the memory which word to work with. After a delay necessitated by the decoder circuit, the appropriate word-select wire will go high, and all others will go low. Only one word-select wire is shown, although there are many of them (4 for the RAM in Fig. 5.9.1). But only one will have the value 1.

Finally, the RAM is ready to store the new value into its flip-flops, so MA is set to 1 to activate memory and the store takes place. After another time delay (shown as memory delay in Fig. 21), at time T3, the output of the RO wires will match what is now stored in the flip-flops, and the store or write operation is complete.