To read a word from memory, the address must be put onto the MAR as before, and the decode delay must be allowed for. By time T4, the appropriate word-select wire is stable at 1 and MA is asserted, causing the output of the appropriate flip-flop to be copied onto the RO wires. This is called the fetch delay. Notice that WR=0 during this time to indicate this is a read operation. Finally, the new value must be stored into the MBR, so MBRLD is strobed by the computer, after which time MBR has the right value. This can be copied by the system into some other register.

The delays are not shown to scale, although in a real memory, the amount of time to copy data into and out of the MBR is usually shorter than the time to copy into or out of RAM, especially if the memory uses tiny capacitors (i.e. it is a DRAM). The longest delays must be taken into account so that the time for one memory cycle is enough for any operation. Making the memory cycle a uniform amount of time, even if a read operation takes less time than a write operation, makes the design of the computer much easier. Designers who want to eke out the last nanosecond of performance from a system may alter this arrangement and use more clever schemes involving non-uniform memory operations, but we will not delve into those advanced topics in this course.