However, MAR-LD is used much more frequently, and in a variety of settings. It is used during the initial instruction fetch part of the machine cycle, which is represented by STATE0. It is also set during the operand fetch step, STATE3, but only when the instruction is one of those that calls for an operand out of memory, namely LOD, ADD, SUB, AND, OR, NOT. Hence an OR gate tells if any of these instructions are being executed, and the output of this gate is ANDed with STATE3 coming out of the DFA so that this is only done at the proper moment in the fetch/decode/execute cycle. This wire is ORed with other conditions, such as STATE0, because the MAR must be loaded at other times. This leads to the complicated circuit shown in Fig. 7.8.2, which is not complete.