Addresses for memory reads (and writes) can only come from the PC register (when a new instruction is being fetched), or the IR register (when the operand's address is hard-coded into the instruction) or from the S register (when the address is computed at run-time.) Only the A register can get the results of an arithmetic calculation, so there must be communication between the A and S registers.

We might think we can shrink our machine a bit by allowing the A register to directly feed into the MAR, thereby doing away with the need for a separate S register. That would work for LDS, where the A register will get a new value anyway. But it would fail for STS, because the address must be available at the same time as the new value to be stored into memory. The PC and IR registers must not be tampered with, so the TMP or MBR registers are the only alternatives. For reasons of simplicity, the CSC-1 chooses not to use either of these, but to have its own separate address register instead, which it calls S. Other computers may do things differently.