Here is the control point sequence for STS, using the "long version" instead of the compressed variants.

      1.     MAR-MUX=01
      2.     MAR-LD=1
      3.     MAR-LD=0;  MA=1;  WR=0;  MBR-MUX=10
      4.     MBR-LD=1
      5.     MBR-LD=0;  MA=0;  PC-INCR=1;  IR-LD=1
      6.     IR-LD=0;  PC-LD=1
      7.     PC-INCR=0;  PC-LD=0          (SAME)
 ------------------------------------------------------
      8.     MAR-MUX=10;  MBR-MUX=01       (NEW)
      9.     MAR-LD=1,  MBR-LD=1
     10.     MAR-LD=0;  MBR-LD=0;  MA=1;  WR=1
     11.     MA=0;  WR=0

This instruction is shorter than ADD since there is no operand fetch stage. Only the lines after the dashed line are different from the ADD instruction; the first seven steps are identical, since they are the instruction fetch stage.

Since STS assumes that S already has the correct address and A already has the correct value to store, it copies these values into the MAR and the MBR respectively in steps 8, 9 and 10, and then starts up the memory in 10. Step 11 merely turns off the memory so that any further changes will not affect it.