Let's go through Fig. 16.6.2 very carefully. After time cycle T1 begins, the CPU begins a read transaction with the memory by setting the address wires to the desired value. Of course, the CPU has already been cleared to do this by the arbiter. In an earlier time phase, not shown in Fig. 16.6.2, the CPU asserted its bus request line and the arbiter decided that it could be the one to control the bus next by asserting the CPU's bus grant line.

The CPU next asserts RD and MA as a way of saying it wants to read and that the memory should become active. All components attached to the bus latch these bus values into their interface registers at the falling edge of T1, right in the middle of that time period. Then decoders go to work and "decide" whether or not that address applies to this component.

Memory responds by beginning its internal work. For the rest of time T1 and the beginning of time T2, the memory fetches the desired word. Then it puts this value onto the data wires just in time for the falling edge of T2 to occur, at which point the CPU latches that value into its interface register. The CPU also negates MA and RD, signaling the end of this bus transaction. By the time T2 is finished, all the bus control wires must be in the same state as they were in the beginning, right after T1 began, so that they will be ready for the next bus initiator to issue a command. This is the end of one bus transaction and the end of two bus cycles.