Fig. 16.6.3 reinforces the idea of registers as go-betweens for the bus and the components. The above bus is called a synchronous bus because all its actions are coordinated by the uniform bus clock signal. Activities such as getting values off the bus can only happen during the transition of the time signal, though some components may put new values onto the bus at other times. But no component "reads" values off the bus until the clock signal makes its downward transition, even though the correct values may be available sooner than that. Synchronous buses are easier to build and debug, although they are a little slower than their cousins, asynchronous buses. |