Chapter 5: Sequential Circuits and Memory
Index of Terms
NOTE: Once you locate the term you want, you can immediately jump to that section of the book by clicking on the number on the right. That merely takes you to the beginning of the section, not necessarily to the place where the term occurs. You can use the browser's find or locate button or menu option to jump to the term.
address................................................. 5.7
address wires........................................... 5.10
arbitration............................................. 5.1
black box............................................... 5.3
bootstrap program....................................... 5.6
byte-addressable........................................ 5.7
byte.................................................... 5.7
cache................................................... 5.6
capacitor............................................... 5.6
chip real estate........................................ 5.6
clock................................................... 5.2
clocked D latch......................................... 5.2
clock input............................................. 5.2
control input........................................... 5.2
control wires........................................... 5.10
data input.............................................. 5.2
data wires.............................................. 5.10
D latch................................................. 5.2
DRAM.................................................... 5.6
EEPROM.................................................. 5.13
EPROM................................................... 5.13
falling edge............................................ 5.4
feedback................................................ 5.1
flip flop............................................... 5.4
fuse.................................................... 5.13
general purpose registers............................... 5.5
gigabyte................................................ 5.8
indeterminate state..................................... 5.1
kilobyte................................................ 5.8
latch................................................... 5.1
leak.................................................... 5.6
least significant bit................................... 5.5
level triggered......................................... 5.4
level triggered......................................... 5.4
LSB..................................................... 5.5
main memory............................................. 5.6
MAR..................................................... 5.7
MBR..................................................... 5.7
megabyte................................................ 5.6
megabyte................................................ 5.8
Memory Address Register................................. 5.7
Memory Buffer Register.................................. 5.7
memory circuit.......................................... 5.1
memory cycles........................................... 5.12
most significant bit.................................... 5.5
MSB..................................................... 5.5
nanosecond.............................................. 5.12
oscillation............................................. 5.1
PLA..................................................... 5.13
PROM.................................................... 5.13
RAM..................................................... 5.6
random access........................................... 5.7
Random Access Memory.................................... 5.6
read.................................................... 5.7
Read Only Memory........................................ 5.6
read operation.......................................... 5.12
refresh circuitry....................................... 5.6
register................................................ 5.5
reset................................................... 5.1
rising edge............................................. 5.4
ROM..................................................... 5.6
schematic............................................... 5.3
set..................................................... 5.1
SRAM.................................................... 5.6
SR latch................................................ 5.1
stable state............................................ 5.1
Static RAM.............................................. 5.6
strobe.................................................. 5.11
terabyte................................................ 5.8
word-addressable........................................ 5.7
word.................................................... 5.7
word-select wires....................................... 5.9
write................................................... 5.7
write operation......................................... 5.12