Chapter 5: Sequential Circuits and Memory
Index of Figures
Fig 5.1.1................SR latch
Fig 5.1.2................initial state of SR latch
Fig 5.1.3................S sets the latch to store a 1
Fig 5.1.4................S changes back to 0; the latch retains its stored 1
Fig 5.1.5................Setting both S and R to 1
Fig 5.1.6................S and R go back to 0, inducing oscillation within the latch
Fig 5.2.1................The D-latch
Fig 5.2.2................The clocked D-latch
Fig 5.3.1................Schematics for latches
Fig 5.3.2................Clocked D-latch storing 1
Fig 5.4.1................Clocked D flip-flop
Fig 5.4.2................Flip-flop (Source: [HAMACH])
Fig 5.4.3................Digital waveforms
Fig 5.4.4................Physical changes in voltage
Fig 5.4.5................The rising edge and the falling edge; only during these times can the contents of the flip-flop change
Fig 5.5.1................A four-bit register using clocked D-latches
Fig 5.5.2................The schematic of a four-bit register
Fig 5.6.1................Capacitors a) shows two plates not touching form a capacitor; b) end-on view of the plates; c) getting charged by a battery d) being discharged by attaching a wire to both plates allowing current to flow briefly
Fig 5.7.1................Schematic of Memory
Fig 5.9.1................RAM using flip-flops
Fig 5.10.1................RAM with MBR
Fig 5.10.2................One-bit slice of the MBR and control circuitry
Fig 5.12.1................Memory cycles
Fig 5.13.1................4-word 3-bit ROM