Chapter 16: Buses
Index of Figures
Fig 16.1.1................A computer system with multiple buses
Fig 16.2.1................Time multiplexing of data wires
Fig 16.4.1................Simple system bus configuration
Fig 16.5.1................Centralized bus control protocol using an arbiter; The CPU requests the bus and gets control over it. Fuzzy gray indicates 1 on the wire.
Fig 16.5.2................Multiple bus initiators contend for the bus; Both I/O controllers request the bus but only one gets control
Fig 16.6.1................Sine wave representing clock pulses 3 Hz = frequency, 1/3 seconds = the period
Fig 16.6.2................Read operation on simplified fictitious bus
Fig 16.6.3................Registers are used to interface with the bus
Fig 16.6.4................Write operation on a synchronous bus
Fig 16.7.1................Read transaction on an asynchronous bus
Fig 16.7.2................Time dependencies of events in an asynchronous bus