Chapter 7: A Simple CPU Architecture
Index of Figures
Fig 7.1.1................Block Diagram of the CSC-1
Fig 7.1.2................Block Diagram of a 16-bit register with load wire
Fig 7.1.3................Super Register with load, clear and increment wires
Fig 7.1.4................Breakdown of the fields of an instruction
Fig 7.7.1................DFA (Deterministic Finite Automaton)
Fig 7.7.2................The control DFA for the CSC-1
Fig 7.7.3................Decoding the CSC-1 instructions
Fig 7.8.1................Hardware DFA corresponding to Fig. 7.7.1
Fig 7.8.2................How state and opcode wires feed into control points