Chapter 7: A Simple CPU Architecture
Index of Terms
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accumulator............................................. 7.1
ALU..................................................... 7.3
arc..................................................... 7.7
block diagram........................................... 7.1
booting................................................. 7.5
clear wire.............................................. 7.1
clock................................................... 7.7
conditional jumps....................................... 7.5
control unit............................................ 7.3
control unit............................................ 7.5
control unit............................................ 7.7
CSC-1................................................... 7.1
deterministic finite automaton.......................... 7.7
DFA..................................................... 7.7
execute stage........................................... 7.5
fetch/decode/execute cycle.............................. 7.5
function................................................ 7.5
functional unit......................................... 7.1
go high................................................. 7.1
graph................................................... 7.7
hardware DFA............................................ 7.8
Hertz................................................... 7.7
Hz...................................................... 7.7
immediate data.......................................... 7.5
immediate instruction................................... 7.5
increment wire.......................................... 7.1
instruction cycle....................................... 7.5
instruction fetch stage................................. 7.5
instruction register.................................... 7.1
jumps................................................... 7.5
load wire............................................... 7.1
machine cycle........................................... 7.5
machine instruction..................................... 7.5
megahertz............................................... 7.7
memory address register................................. 7.1
memory buffer register.................................. 7.1
MHz..................................................... 7.7
mnemonics............................................... 7.2
node.................................................... 7.7
opcode.................................................. 7.1
operand fetch stage..................................... 7.5
operation decoding stage................................ 7.5
PC register............................................. 7.1
procedure............................................... 7.5
program counter......................................... 7.1
registers............................................... 7.1
register transfer language.............................. 7.4
RTL..................................................... 7.4
secondary register...................................... 7.1
state................................................... 7.7
state register.......................................... 7.8
subprogram.............................................. 7.5
subroutine.............................................. 7.5
transitions............................................. 7.7
unconditional jumps..................................... 7.5